View MTV24C08_577116.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MTV24C08/ MYSON 24LC08 TECHNOLOGY (Preliminary) 2-Wire 8912-Bit Serial CMOS EEPROM
FEATURES
* State- of- the- Art Architecture - Non-volatile data storage - Standard Voltage and Low Voltage Operation 5.0(Vcc = 4.5V to 5.5V) for MTV24C08 3.0(Vcc = 2.7V to 5.5V) for 24LC08 2 wire I2C serial interface - Provides bidirectional data transfer protocol 16-byte page write mode - Minimizes total write time per word Self-timed write-cycle(including auto-erase) Durable and Reliable - 10 years data retention after 1000K write/erase cycles - Minimum of 1,000,000 write/erase cycles per word - Unlimited read cycles - ESD protection Low standby current
* * * *
*
GENERAL DESCRIPTION
The MTV24C08/24LC08 is a low cost, non-volatile, 4096-bit serial EEPROM with enhanced security device and conforms to all specifications in I2C 2 wire protocol. The whole memory can be disabled (Write Protected) by connecting the WP pin to Vcc. This section of memory then becomes unalterable unless WP is switched to Vss. It is enhanced with security function. Every word of the memory has a programmable security bit to permit whether it can be altered or not. The MTV24C08/24LC08's communication protocol uses CLOCK(SCL) and DATA I/O(SDA) lines to synchronously clock data between the master (for example a microcomputer)and the slave EEPROM devices(s) .In addition, the bus structure allows for a maximum of 16K of EEPROM memory. This supports the family in 2K, 4K, 8K, 16K devices, allowing the user to configure the memory as the application requires with any combination of EEPROMs (not to exceed 16K). MTV EEPROMs are designed and tested for application requiring high endurance, high reliability, and low power consumption.
This datasheet contains new product information. Analog Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product. MTV24C08/24LC08 Revision.1.0 11/03/1999 1/15
MYSON TECHNOLOGY
BLOCK DIAGRAM
WP
MTV24C08/ 24LC08 (Preliminary)
start cycle
SDA SCL
START STOP LOGIC
load
CONTROL LOGIC
ck inc
H.V. GENERATION TIMING & CONTROL
A0 A1 A2
SLAVE ADDRESS REGISTER & COMPARATOR
WORD ADDRESS COUNTER
6
64
EEPROM ARRAY DATA BIT 64X16X8
XDEC
128 4 R/W ~ , device address bit A0
YDEC
128
VCC VSS
Din
DATA REGISTER
DOUT ACK
Dout
MTV24C08/24LC08 Revision.1.0 11/03/1999 2/15
MYSON TECHNOLOGY
PIN DESCRIPTIONS
SERIAL CLOCK (SCL) The SCL input is used to clock all data into and out of the device.
MTV24C08/ 24LC08 (Preliminary)
SERIAL DATA (SDA) SDA is a bidirection pin used to transfer data or security bit into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. Thus, the SDA bus requires a pull-up resistor to Vcc (typical 4.7K [ for 100KHZ, 1K [ for 400KHZ) DEVICE ADDRESS INPUTS (A0, A1, A2) Device address pin A2 are connected to Vcc or Vss to configure the EEPROM address. The following table (Table A) shows the active pins across the 24C/LCXX device family. TABLE A Device 24C02/24LC02 24C04/24LC04 MTV24C08/24LC08 24C016/24LC016 A0 ADR XP XP XP A1 ADR ADR XP XP A2 ADR ADR ADR XP
ADR indicates the device address pin. XP indicates that device address pin don' t care but refers to an internal PAGE BLOCK memory segment. WRITE PROTECTION (WP) If WP is connected to Vcc, PROGRAM operation onto the whole memory will not be executed. READ operations are possible. If WP is connected to Vss, normal memory operation is enabled, READ/WRITE over the entire memory is possible.
1.0 FUNCTIONAL DESCRIPTION
1.1 APPLICATIONS MTV' s electrically erasable programmable read only memories (EEPROMs) offer valuable security features including write protect function , two write modes ,three read modes, and a wide variety of memory size. Typical applications for the I2C bus and 24C/LCXX memories are included in SANs(small-area-networks), stereos, televisions, automobiles and other scaled-down systems that don't require tremendous speeds but instead cost efficiency and design simplicity. 1.2 ENDURANCE AND DATA RETENTION The MTV24C08/24LC08 is designed for applications requiring up to 1,000,000 programming cycles (BYTE WRITE and PAGE WRITE). It provides 10 years of secure data retention, without power after the execution of 1,000,000 programming cycles.
1.3 DEVICE OPERATION
MTV24C08/24LC08 Revision.1.0 11/03/1999 3/15
MYSON TECHNOLOGY
MTV24C08/ 24LC08 (Preliminary)
The MTV24C08/24LC08 support a bi-directional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is the master and the device that is controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the MTV24C08/24LC08 is considered a slave in all applications. Clock And Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. (Shown in Figures 1 and 2) Start Condition A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition. (Shown in Figure 2) Stop Condition A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition. (Shown in Figure 2) Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. The device that acknowledges, has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. (Shown in Figure 3) Devices Addressing After generating a START condition, the bus master transmits the slave address consisting of a 4-bit device code (1010) for the MTV24C08/24LC08, 3-bit device address (A2 A1 A0) and 1-bit value indicating the read or write mode. All I2C EEPROMs use and internal protocol that defines a PAGE BLOCK size of 8K bits. The MTV24C08/24LC08 contains four 2K-bits PAGE BLOCK, and the device address bits A0 and A1 are used for determinating which PAGE BLOCK of memory segment the read/write operation will be proceeded in. The eighth bit of slave address determines if the master device wants to read or write to the MTV24C08/24LC08. (Refer to table B). The MTV24C08/24LC08 monitor the bus for its corresponding slave address all the time. It generates an acknowledge bit if the slave address was true and it is not in a programming mode. TABLE B Operation Read Write
Control Code 1010 1010
Chip Select A2 A1 A0 A2 A1 A0
R/W 1 0
A2 are used to access device address for MTV24C08/24LC08, 8K bits' size device. A0 ,A1are used to access page blocks ,size of 8K bits, in the MTV24C08/24LC08
MTV24C08/24LC08 Revision.1.0 11/03/1999 4/15
MYSON TECHNOLOGY
WRITE OPERATIONS
MTV24C08/ 24LC08 (Preliminary)
Byte Write Following the start signal from the master, the slave address is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore the next byte transmitted by the master is the word address and will be written into the address pointer of the MTV24C08/24LC08. After receiving another acknowledge signal from the MTV24C08/24LC08 the master device will transmit the data word to be written into the addressed memory location. The MTV24C08/24LC08 acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this period the MTV24C08/24LC08 will not generate acknowledge signals. (Shown in Figure 4) Page Write The write control byte, word address and the first data byte are transmitted to the MTV24C08/24LC08 in the same way as in a byte write. But instead of generating a stop condition the master transmit up to 16 data bytes to the MTV24C08/24LC08 which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a stop condition. After the receipt of each byte, the two lower order address pointer bits are internally incremented by one. The higher order six bits of the word address remains constant. If the master should transmit more than 16 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received an internal write cycle will begin. (Shown in Figure 5). Acknowledge Polling Since the device will not acknowledge during a write cycle , this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughout). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle , then no ACK will returned. If the cycle is complete then the device will return the ACK and the master can then proceed with the next read or write commands. Write Protection Programming will not take place if the WP pin of the MTV24C08/24LC08 is connected to Vcc. The MTV24C08/24LC08 will accept slave and byte addresses; but if the memory accessed is write protected by the WP pin, the MTV24C08/24LC08 will not generate an acknowledge after the first byte of data has been received, and thus the programming cycle will not be started when the stop condition is asserted. READ OPERATIONS Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read, and sequential read.
MTV24C08/24LC08 Revision.1.0 11/03/1999 5/15
MYSON TECHNOLOGY
MTV24C08/ 24LC08 (Preliminary)
Current Address Read The MTV24C08/24LC08 contains an address counter that maintains the address of the last accessed word, internally incremented by one. Therefore if the previous access (either a read or write operation ) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to one, the MTV24C08/24LC08 issues an acknowledge and transmits the eight bit data word . The master will not acknowledge the transfer but does generate a stop condition and the MTV24C08/24LC08 discontinues transmission. (Shown in Figure 6) Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the MTV24C08/24LC08 as part of a write operation. After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with R/W bit set to a one. The MTV24C08/24LC08 will then issue an acknowledge and transmit the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the MTV24C08/24LC08 discontinues transmission. (Shown in Figure 7) Sequential Read Sequential reads are initiated by either a current address read or a random read. After the master receives a data word, it responds with an acknowledge. As long as the E2PROM receives an acknowledge, it will continue to increment the data words. When the memory address limit is reached, the data word address will " roll over" and the sequential read will continue. The sequential read operation is terminated when the master does not respond with a zero but does generate a following stop condition.
2.0 CONNECTION DIAGRAM
MTV24C08/24LC08 Revision.1.0 11/03/1999 6/15
MYSON TECHNOLOGY
MTV24C08/ 24LC08 (Preliminary)
A0 A1 A2 VSS
1 2
8
VCC WP SCL SDA
A0 A1 A2 VSS
1 2
8
VCC WP SCL SDA
24C08 7 or 3 24LC08 6 4 Dual-In-Line package 5
24C08 7 or 3 24LC08 6 4 5
SO package (M8) 8 VCC WP SCL SDA
A0 A1 A2 VSS
1 2 3 4 TSSOP 24C08 or 24LC08
7 6 5
Pin Name A0, A1 A2 Vss SDA SCL WP Vcc N.C. Device Address inputs Ground Data I/O Clock input Write Protect + 5 V or + 3 V
3.0 ABSOLUTE MAXIMUM RATINGS
Storage Temperature................................-65C to + 125C Voltage with Respect to Ground.................-0.3 to + 6.5 V NOTE: These are STRESS rating only. Appropriate conditions for operating these devices given elsewhere may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability.
4.0 OPERATING CONDITIONS
Temperature under bias: MTV24C08/24LC08.......0C to + 70C MTV24C08/24LC08-I.....-40C to + 85C
MTV24C08/24LC08 Revision.1.0 11/03/1999 7/15
MYSON TECHNOLOGY
5.0 ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS (Vcc =5V +/- 10% ,MTV24C08/24LC08 F cc =3V +/- 10% ,24LC08) V MTV24C08/ 24LC08 Min Max -- 10 -- -- -1 -1 -0.1 2 -- 2.4 --
VCC-0.2
Default
MTV24C08/ 24LC08 (Preliminary)
Symbol ICC1 ICC2 ISB IIL IOL VIL VIH VOL1 VOH1 VOL2 VOH2 VLK
Parameter
Operating Current (Program) Operating Current (Read) Standby Current Input Leakage Output Leakage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage VCC Lockout Voltage
Conditions
SCL = 100KHZ CMOS Input Levels SCL = 100KHZ CMOS Input Levels SCL = SDA = 0 V VIN = 0 V to VCC VOUT = 0 V to Vcc
24LC08 Min -- -- -- -1 -1 -0.1
0.8VCC
Units mA mA A A A V V V V V V V
Max 8 2 10 +1 +1
0.15 VCC VCC+0.2
2 10 +1 +1 0.8
VCC +0.2
IOL = 2.1mA TTL IOH = -400uA TTL IOL = 10uA CMOS IOH = -10uA CMOS Programming Command Can Be Executed
0.4 -- 0.2 -- --
-- 2.4 --
VCC-0.2
Default
0.4 -- 0.2 -- --
6.0 SWITCHING CHACTERISTICS (Under Operating Conditions )
AC ELECTRICAL CHARACTERISTICS (Vcc =5V +/- 10% , MTV24C08 F cc =3V +/- 10% ,24LC08) V (Vcc =5V +/- 10% , MTV24C08 Fast Mode) MTV24C08/ 24LC08 Min Max 0 100 4000 -- 4700 -- -- 1000 -- 300 4000 -- 4700 -- 0 -- 250 -- 4000 -- 300 3500 4700 -- 300 -- -- --
8/15
Parameter Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time START condition hold time START condition setup time Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time Data out hold time Input filter spike suppression (SDA and SCL pins) Write cycle time
Symbol Fscl Thigh Tlow Tr Tf Thd:Sta Tsu:Sta Thd:Dat Tsu:Dat Tsu:Sto Taa Tbuf Tdh Tsp Twr
MTV24C08 (Fast Mode) Min Max -- 400 600 -- 1200 -- -- 300 -- 300 600 -- 600 -- 0 -- 100 -- 600 -- 100 900 1200 -- 50 -- -- -- 50 10
Units kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ms
100 10
MTV24C08/24LC08 Revision.1.0 11/03/1999
MYSON TECHNOLOGY
CAPACITANCE TA= 25C , f=250KHZ Symbol CO
UT
MTV24C08/ 24LC08 (Preliminary)
Parameter Output capacitance Input capacitance
Max 5 5
Units pF pF
CIN A.C. Conditions of Test
Input Pulse Levels Input Rise and Fall times Input and Output Timming level Output Load
Vcc x 0.1 to Vcc x 0.9 10 ns Vcc x 0.5 1 TTL Gate and CL = 100pf
7.0TIMING DIAGRAM
BUS TIMING
Tf Tlow Thigh Tr Tlow
SCL
Thd:Sta Tsu:Dat Tsu:Sta Thd:Dat Tsu:Sta
SDA IN
Tbuf
Taa
Tdh
SDA OUT
SDA
SCL
DATA STABLE DATA CHANGE
Figure 1. Data Validity
MTV24C08/24LC08 Revision.1.0 11/03/1999 9/15
MYSON TECHNOLOGY
MTV24C08/ 24LC08 (Preliminary)
SDA
SCL
START
BIT
STOP
BIT
Figure 2. Definition of Start and Stop
SCL FROM MASTER 1 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE 8 9
Figure 3. Acknowledge Response from Receiver
S T A R T S A C K A C K A C K SLAVE ADDRESS BYTE ADDRESS DATA n S T O P
BUS ACTIVITY MASTER
SDA LINE
P
BUS ACTIVITY SLAVE
Figure 4. Byte Write for Data
S T A R T S A C K A C K A C K A C K SLAVE ADDRESS BYTE ADDRESS n DATA n DATA n+15 S T O P P
BUS ACTIVITY MASTER
SDA LINE
BUS ACTIVITY SLAVE
Figure 5. Page Write for Data
MTV24C08/24LC08 Revision.1.0 11/03/1999 10/15
MYSON TECHNOLOGY
MTV24C08/ 24LC08 (Preliminary)
BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY SLAVE
S T A R T s
SLAVE ADDRESS
S T O P
P A C K
DATA
Figure 6. Current Address Read for Data
BUS ACTIVITY MASTER SDA LINE S T A R T S A C K A C K SLAVE ADDRESS BYTE ADDRESS n S T A R T SLAVE ADDRESS S T O P P A C K
S
BUS ACTIVITY SLAVE
DATA n
Figure 7. Random Read for Data
S T A R T S A C K DATA n DATA n+1 DATA n+x SLAVE ADDRESS S T O P P
BUS ACTIVITY MASTER
A C K
A C K
SDA LINE
BUS ACTIVITY SLAVE
A C K
Figure 8. Sequential Read for Data
MTV24C08/24LC08 Revision.1.0 11/03/1999 11/15
MYSON TECHNOLOGY
9.0 PACKAGE DIAGRAMS Plastic Dual-in-line Package (PDIP)
D
MTV24C08/ 24LC08 (Preliminary)
E-PIN O0.118 NOTE 9
E1
PIN #1 INDENT O0.025 DEEP 0.006-0.008
E 7 (4X) 15 (4X) A2 B S e B1 B2 A1 A L
C eB
SYMBOLS A A1 A2 B B1 B2 C D E E1 e L eB S
DIMENSIONS IN MILLIMETERS MIN NOM MAX 5.33 0.38 3.25 3.30 3.45 0.36 0.46 0.56 1.14 1.27 1.52 0.18 0.99 1.17 0.20 0.25 0.33 9.12 9.30 9.53 7.62 8.26 6.20 6.35 6.60 2.54 3.18 8.38 9.40 0.71 0.84 0.97
DIMENSIONS IN INCHES MIN NOM MAX 0.210 0.015 0.128 0.130 0.136 0.014 0.018 0.022 0.045 0.050 0.060 0.032 0.039 0.046 0.008 0.010 0.013 0.359 0.366 0.375 0.300 0.325 0.244 0.250 0.260 0.100 0.125 0.330 0.370 0.028 0.033 0.038
MTV24C08/24LC08 Revision.1.0 11/03/1999 12/15
MYSON TECHNOLOGY
JEDEC Small Outline Package(SO-8)
MTV24C08/ 24LC08 (Preliminary)
E
H
L
VIEW "A"
D 7 (4X)
0.015x45
7 (4X)
A2
A
C
e
VIEW "A" y A1 B
SYMBOLS A A1 A2 B C D E e H L y c
DIMENSIONS IN MILLIMETERS MIN NOM MAX 1.47 1.60 1.73 0.10 0.25 1.45 0.33 0.41 0.51 0.19 0.20 0.25 4.80 4.85 4.95 3.81 3.91 3.99 1.27 5.79 5.99 6.20 0.38 0.71 1.27 0.10 0O 8O
DIMENSIONS IN INCHES MIN NOM MAX 0.058 0.063 0.068 0.004 0.010 0.057 0.013 0.016 0.020 0.0075 0.008 0.0098 0.189 0.191 0.195 0.150 0.154 0.157 0.050 0.228 0.236 0.244 0.015 0.028 0.050 0.004 0O 8O
MTV24C08/24LC08 Revision.1.0 11/03/1999 13/15
MYSON TECHNOLOGY
8L TSSOP PACKAGE OUTLING DRAWING
MTV24C08/ 24LC08 (Preliminary)
E1 PIN 1 INDICATOR O0.70 SURFACE POLISHED
E
L
L1
DETAIL A D
e A2
E1
L1
A1
y
SYMBOLS A A1 A2 b C D E E1 e L L1 y c
DIMENSIONS IN MILLIMETERS MIN NOM MAX 1.05 1.10 1.20 0.05 0.10 0.15 1.00 1.05 0.20 0.25 0.28 0.127 2.90 3.05 3.10 6.20 6.40 6.60 4.30 4.40 4.50 0.65 0.50 0.60 0.70 0.90 1.00 1.10 0.10 0O 4O 8O
C
b
A
DETAIL A
MTV24C08/24LC08 Revision.1.0 11/03/1999 14/15

▲Up To Search▲

Price & Availability of MTV24C08

	To Download MTV24C08 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .